linerneeds.blogg.se - Berkeley upc benchmark uts

A dialect of PGAS languages (Partitioned Global Address Language).dominated by the wait for memory fetches borrowed: Andrew Lumsdaine, Douglas Gregor Low level Low level Express Parallelism Express Parallelism tedious memory latency dominated Memory latency dominated Communication dominated.explore the structure, not computation.data access patterns has less locality.Data partitioning is not suitable, may lead to load balancing.Unstructured and highly irregular data structure.Computation partitioning is not suitable.Parallelism cannot be exploited statically.Nested task parallelism, task mapping until launching timeĬhallenges in Efficient Parallel Graph Processing.Abstraction on memory hierarchies: hierarchical place tree (Habanero-java).Parallel operators: map parallelism statically.Data type for hierarchical tiled array (multiple level tiling).Recursive task tree, static mapping for tasks.

Explicitly tune the data layout and data transfer (Parallel memory hierarchy).

Mapping Hierarchical Parallelism to Modern Supercomputers

Discrete interconnection: data int, OS int, global Sync.

Global address space, through HPP controller.

HPP Interconnect of Dawning 6000 HPP Architecture of Dawning7000 Traditional cluster

Intra-node parallelism should be well exploited.

Many-core accelerators Harpertown Dunnington.

Shared work list for irregular applicationsĭeep Memory Hierarchies in Modern Computing Platforms.

Exploit hierarchical data parallelism for regular applications.Exploit the tiered network of Dawning 6000.E N D - Presentation TranscriptĮxploiting the Potential of Modern Supercomputers Through High Level Language Abstractions Exploit Hierarchical and Irregular Parallelism in UPC Li Chen State Key Laboratory of Computer Architecture Institute of Computing Technology, CASĮxploit Hierarchical and Irregular Parallelism in UPC-H